Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy mode
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United States of America Patent
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Dec 25, 2018
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app pub date -
Sep 30, 2016
filing date -
Sep 30, 2016
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Abstract
Embodiments of the invention provide an approach to implement a single architecture to support high bandwidth memory of pseudo channel mode or legacy channel mode by using a single command channel and single data channel. An address mapping method forces each port transaction to alternatively split to two pseudo channels. Compared to the conventional pseudo channel architecture, the single architecture and pseudo channel rotation eliminates the need for duplicated command traffic logic, and a time division command arbitrator, which greatly reduces both control logic and power consumption of the circuits. Furthermore, pseudo channel rotation improves the utilization of memory bandwidth because the address mapping improves synchronization of the two pseudo channel traffics.
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