Method of selectively depositing a metal layer in an opening in a dielectric layer by forming a metal-deposition-prevention layer around the opening of the dielectric layer
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United States of America Patent
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Aug 13, 2002
Grant Date -
N/A
app pub date -
Aug 2, 2001
filing date -
Mar 21, 2001
priority date (Note) -
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Abstract
A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.
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