Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors
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United States of America Patent
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Aug 14, 2007
Grant Date -
N/A
app pub date -
Dec 21, 2004
filing date -
Dec 22, 2003
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Abstract
In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H.sub.2 or H.sub.2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.
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