Erase verifying method of NAND flash memory device
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United States of America Patent
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Oct 20, 2009
Grant Date -
Oct 9, 2008
app pub date -
Dec 29, 2007
filing date -
Apr 6, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In an erase verifying method of a NAND flash memory device, a power supply voltage (Vcc) is applied to a second bit line while precharging a first bit line to a first positive voltage. Select transistors are turned on, and a ground voltage is applied to word lines of memory cell transistors. A second positive voltage is applied to source lines to which sources of the select transistors and the memory cell transistors are connected. An erased state of the memory cell transistor is verified according to whether charges accumulated in the first bit line are discharged.
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