Stacked MOS device with means to prevent substrate floating

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United States of America Patent

PATENT NO 4571609
SERIAL NO

06596561

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An MOS type semiconductor device having a semiconductor substrate, an insulating layer formed in or on said semiconductor substrate, and an MOS transistor formed on said insulating layer, characterized in that said insulating layer is formed at a region below said MOS transistor excluding at least part of the region below a channel region of said MOS transistor.

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Patent Owner(s)

  • TOKYO SHIBAURA DENKI KABUSHIKI KAISHA;KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hatano, Hiroshi Yokohama, JP 61 409

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