Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications
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United States of America Patent
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May 17, 2011
Grant Date -
Jan 20, 2011
app pub date -
Sep 27, 2010
filing date -
Jan 12, 2007
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Abstract
A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
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