Dynamic test program generator for VLIW simulation
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United States of America Patent
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Aug 1, 2006
Grant Date -
Aug 22, 2002
app pub date -
Feb 20, 2001
filing date -
Feb 20, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.
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