State table complexity reduction in a hierarchical verification flow

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United States of America

PATENT NO 11222154
APP PUB NO 20210110093A1
SERIAL NO

17063059

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Abstract

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State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.

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Patent Owner(s)

  • SYNOPSYS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Allen, David L Fremont, US 63 1365
Bansal, Sachin Noida, IN 11 320
De, Kaushik Pleasanton, US 18 182
Gulati, Sanjay New Delhi, IN 7 91
Kulatunga, Malitha Colombo, LK 1 0
Mukherjee, Rajarshi San Jose, US 25 352
Pal, Bhaskar Bangalore, IN 11 28
Patel, Nishant Milpitas, US 14 37
Pratap, Gaurav Noida, IN 3 0

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