FIFO memory device capable of writing contiguous data into rows
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United States of America Patent
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Apr 30, 1996
Issued Date -
N/A
app pub date -
Feb 21, 1995
filing date -
Mar 17, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
A FIFO memory device includes a storage device and an address translator. The storage device contains a plurality of FIFO storage unit cells connected in parallel, wherein data is input to and output from each of the FIFO storage unit cells one word at a time, and data is input to the storage device one word at a time and output from the storage device in units of a plurality of words. The address translator is disposed between a central processing unit and an input side of the storage device for translating an address specified by the central processing unit into an address specifying one of the storage unit cells of the storage device. The address translator includes a count enable signal output element responsive to addressing from the central processing unit for outputting a count enable signal, a counter responsive to the count enable signal from the count enable signal output element for counting up, and a selector responsive to a count value of the counter for selecting one of the storage unit cells.
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