Semiconductor module for stacking and stacked semiconductor module

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United States of America Patent

PATENT NO 8716868
APP PUB NO 20100295186A1
SERIAL NO

12783836

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Abstract

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A pad (15) is provided on a surface connecting a first substrate (11) of a lower layer module with an upper layer module, the pad is partially covered by an insulating film (20) to form an opening section (3) exposing the pad (15), a first connection terminal (2) is formed on the lower surface of the first substrate (11) of the lower layer module, the planar shape of the opening section (3) is different from the planar shape of the first connection terminal (2), the outer shape of the opening section (3) is larger than the first connection terminal (2), and in a transmissive inspection from above, the shape of the lower end of a second connection terminal (30) spreading in the opening section (3) is not concealed by the other terminal. This configuration enables easy and reliable determination of whether bonding sections are satisfactory by a non-destructive inspection.

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Patent Owner(s)

  • PANASONIC CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kawabata, Takeshi Osaka, JP 104 1209
Yui, Takashi Shiga, JP 30 283

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