Electronic design 3D mixed placement and unfolding

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United States of America Patent

PATENT NO 11436402
SERIAL NO

17219695

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Abstract

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Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.

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Patent Owner(s)

  • CADENCE DESIGN SYSTEMS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Deng, Liqun Shanghai, CN 15 51
Liu, Miao Shanghai, CN 66 179
Xu, Guozhi Shanghai, CN 2 3

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