Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines

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United States of America Patent

PATENT NO 10372454
APP PUB NO 20170068534A1
SERIAL NO

15354742

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Abstract

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A method for allocation of a segmented interconnect in an integrate circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. The method also comprises contending for the plurality of resources in accordance with requests from the plurality of resource consumers. Finally, the method comprises accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of global segment buses.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Abdallah, Mohammad El Dorado Hills, US 131 2793

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