Memory data bus structure and method of transferring information with plural memory banks
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United States of America Patent
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Apr 15, 2008
Grant Date -
Jul 12, 2007
app pub date -
Jan 9, 2006
filing date -
Jan 9, 2006
priority date (Note) -
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Abstract
A data bus structure for a dynamic random access memory (DRAM) according to the present invention includes a series of data buses, each shared by a plurality of memory banks, and a switching device to selectively couple the data buses to a global data bus to enable the memory device to provide and receive data. The data bus structure conserves space on a chip or die and prevents significant timing skews for data accessed from different memory banks.
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