Integrated bipolar-CMOS circuit isolation process for providing different backgate and substrate bias
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United States of America Patent
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Mar 27, 1990
Issued Date -
N/A
app pub date -
Jan 6, 1989
filing date -
May 28, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Disclosed is a proces for making a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.
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