Tri-gate transistor device with stress incorporation layer and method of fabrication
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United States of America Patent
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May 11, 2010
Grant Date -
Nov 23, 2006
app pub date -
Jul 25, 2006
filing date -
Jun 27, 2003
priority date (Note) -
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Abstract
A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
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