Grid refinement method

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United States of America Patent

PATENT NO 8822106
SERIAL NO

13722266

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Abstract

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The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is 1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Burn Jeng Hsinchu, TW 122 3088
Lin, Shy-Jay Jhudong Township, Hsinchu County, TW 129 850
Liu, Pei-Yi Changhua, TW 30 234
Shin, Jaw-Jung Hsinchu, TW 43 691
Wang, Wen-Chuan Hsinchu, TW 71 471

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