Method and apparatus for generating technology independent delays
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United States of America Patent
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Dec 9, 2008
Grant Date -
Jun 7, 2007
app pub date -
Dec 2, 2005
filing date -
Dec 2, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for generating an integrated circuit (IC) is provided wherein signal delays are transferable across two synthesis libraries where each library is associated with a different IC fabrication process. The method initiates with describing an IC design through a hardware description language (HDL). The method includes identifying logic signal delay points within the HDL. Then, technology-independent logic signal delay code is inserted within the delay points of the HDL representation. A system for designing an IC is also provided.
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