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Abstract

An augmenting circuit (153) augments an embedded PN sequence of 2.sup.N -1 chips generated by an N-bit LSSR (111) to provide an augmented PN sequence of 2.sup.N chips and an augmented PN sequence of 2.sup.N chips shifted by D chips. The augmenting circuit comprises a N-bit counter (123) that counts a plurality of clock bits. The N-bit counter provides a pre-carry signal that changes state when the counter's index equals a predetermined value and provides a value of the N-k most-significant-bits (MSB) of the index. A logic circuit (107,119) receives the plurality of clock bits and responds to the pre-carry signal to gate the plurality of clock bits. A comparator (135) receives the value of the N-k MSB and a threshold value to output a select signal that controls a multiplexer (139).

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