Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors
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United States of America Patent
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Mar 11, 2003
Grant Date -
Oct 24, 2002
app pub date -
Apr 19, 2001
filing date -
Apr 19, 2001
priority date (Note) -
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Abstract
A method for forming a heterojunction bipolar transistor includes forming two sets of spacers on the sides of an emitter pedestal. After the first set of spacers is formed, first extrinsic base regions are implanted on either side of an intrinsic base. The second set of spacers is formed on the first set of spacers. Second extrinsic base regions are then implanted on respective sides of the intrinsic base. By using two sets of spacers, the first and second extrinsic base regions have different widths. This advantageously brings the combined extrinsic base structure closer to the emitter of the transistor but not closer to the collector. As a result, the base parasitic resistance is reduced along with collector-to-extrinsic base parasitic capacitance. The performance of the transistor is further enhanced as a result of the extrinsic base regions being self-aligned to the emitter and collector.
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