Shallow Trench Isolation Structures in Semiconductor Device and Method for Manufacturing the Same
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United States of America Patent
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Jan 12, 2016
Grant Date -
Jan 28, 2016
app pub date -
Aug 12, 2014
filing date -
Jul 24, 2014
priority date (Note) -
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Abstract
Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed.
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