Vector compare and store instruction that stores index values to memory

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United States of America Patent

PATENT NO 11163564
SERIAL NO

16154404

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Abstract

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The present disclosure is directed to methods to generate a packed result array using parallel vector processing, of an input array and a comparison operation. In one aspect, an additive scan operation can be used to generate memory offsets for each successful comparison operation of the input array and to generate a count of the number of data elements satisfying the comparison operation. In another aspect, the input array can be segmented to allow more efficient processing using the vector registers. In another aspect, a vector processing system is disclosed that is operable to receive a data array, a comparison operation, and threshold criteria, and output a packed array, at a specified memory address, comprising of the data elements satisfying the comparison operation.

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Patent Owner(s)

  • VERISILICON MICROELECTRONICS (SHANGHAI) CO., LTD.; VERISILICON HOLDINGS CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bezet, Charles R Rowlett, US 1 2
Stewart, Charles H Richardson, US 12 243

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