Twin gate tunnel field-effect transistor (FET)

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United States of America Patent

PATENT NO 11557663
SERIAL NO

16661052

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Abstract

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A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINE CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Balakrishnan, Karthik Scarsdale, US 334 2019
Hekmatshoartabari, Bahman White Plains, US 389 1807
Reznicek, Alexander Troy, US 1406 11120
Yau, Jeng-Bang Yorktown Heights, US 144 1325

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