Method and apparatus for performing multiplier regularization
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United States of America Patent
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Sep 6, 2022
Grant Date -
Apr 25, 2019
app pub date -
Dec 12, 2018
filing date -
Dec 12, 2018
priority date (Note) -
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Abstract
A method for implementing a multiplier on a programmable logic device (PLD) is disclosed. Partial product bits of the multiplier are identified and how the partial product bits are to be summed to generate a final product from a multiplier and multiplicand are determined. Chains of PLD cells and cells in the chains of PLD cells for generating and summing the partial product bits are assigned. It is determined whether a bit in an assigned cell in an assigned chain of PLD cells is under-utilized. In response to determining that a bit is under-utilized, the assigning of the chains of PLD cells and cells for generating and summing the partial product bits are changed to improve an overall utilization of the chains of PLD cells and cells in the chains of PLD cells.
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