Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same

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United States of America Patent

PATENT NO 6995427
APP PUB NO 20040150006A1
SERIAL NO

10763978

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Abstract

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A semiconductor structure having a high-strained crystalline layer with a low crystal defect density and a method for fabricating such a semiconductor structure are disclosed. The structure includes a substrate having a first material comprising germanium or a Group (III)-Group (V)-semiconductor or alloy thereof. In addition, a crystalline epitaxial first layer, comprising a graded buffer layer and a substantially relaxed layer, is provided. The buffer layer is sufficiently relaxed to provide relaxation of the substantially relaxed layer deposited thereon. A further layer may be provided on the first layer, and the transfer of at least the further layer is facilitated by providing a weakened zone in the first layer.

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Patent Owner(s)

  • SOITEC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aulnette, Cecile Grenoble, FR 31 427
Dupont, Frederic Grenoble, FR 11 170
Mazure, Carlos Saint Nazaire les Eymes, FR 63 1064

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