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United States of America Patent

PATENT NO 7259468
APP PUB NO 20050242418A1
SERIAL NO

10835571

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Abstract

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The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDNO 8 LI-HSIN RD VI HSINCHU SCIENCE PARK HSINCHU 300

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Yang, Wen-Kun Hsinchu, TW 109 2667

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