Integrated circuit packaging system with filled vias and method of manufacture thereof
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United States of America Patent
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Jun 18, 2013
Grant Date -
Sep 27, 2012
app pub date -
Mar 24, 2011
filing date -
Mar 24, 2011
priority date (Note) -
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Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a via hole in the substrate, the via hole having a top end and a bottom end with the bottom end is larger than the top end; forming a pad on the substrate, the pad encloses the top end of the via hole; and reflowing a conductive filler having higher volume than the via hole over the via hole, the conductive filler having a protrusion extending from the bottom end and the bottom end entirely overlaps at least one surface of the protrusion.
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