Programmable logic array integrated circuits with enhanced output routing
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United States of America Patent
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Feb 25, 1997
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N/A
app pub date -
Jun 30, 1995
filing date -
Nov 4, 1994
priority date (Note) -
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Abstract
A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A general interconnect structure (20, 30) is provided for interconnecting a LAB with other LABs. A LAB-based interconnect structure (24, 26) is provided for connecting inputs of the LEs in a LAB to a subset of the general interconnect. One or more of output signal lines (55) are included in the LAB-based interconnect structure and are connectable to device output pins. A digital information processing system incorporating the invention is disclosed.
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