Circuit and method for generating data input buffer control signal
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United States of America Patent
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Jul 17, 2012
Grant Date -
Feb 25, 2010
app pub date -
Jun 24, 2009
filing date -
Aug 20, 2008
priority date (Note) -
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Abstract
A data input buffer control signal generating device is capable of preventing unnecessary operation and current consumption of blocks and thus stabilizing an internal operation of DRAM by generating a control signal which controls an enabling timing of a data input buffer not to be conflicted with an output data. The data input buffer control signal generating device includes a write-related control unit configured to generate a data input buffer reference signal generated on the basis of a write latency by a write command, a read-related control unit configured to replicate a delay through a data output path, delay an end command for a data output termination and generate a delayed end command, wherein the end command is generated by a read command, and an output unit configured to output a data input buffer control signal by combining the data input buffer reference signal and the output of the delayed end command.
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