Insulated gate e-mode transistors
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United States of America Patent
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Dec 14, 2010
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N/A
app pub date -
Nov 26, 2008
filing date -
Dec 10, 2007
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Abstract
Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region.
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