System level mechanism for invalidating data stored in the external cache of a processor in a computer system
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United States of America Patent
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Apr 7, 1998
Grant Date -
N/A
app pub date -
Feb 12, 1997
filing date -
Mar 31, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.
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