Memory with improved command/address bus utilization

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11934326
APP PUB NO 20220391334A1
SERIAL NO

17882550

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Abstract

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Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alexander, Kyle Boise, US 6 8
Bell, Debra M Boise, US 100 1046
Howe, Gary L Allen, US 48 298
Johnson, Vaughn N Boise, US 5 8
Pecha, Brian T Boise, US 5 8
Wiscombe, Miles S Boise, US 12 24

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