Device for protection against the formation of parasitic transistors in an integrated circuit for driving an inductive load
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United States of America Patent
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-
Jul 21, 1992
Grant Date -
N/A
app pub date -
Jul 17, 1990
filing date -
Jul 25, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A monolithic integrated circuit (M) includes a power device (Q3, Q4) for driving an inductive load (L) and a control device for the power device. The control device comprises a voltage limiting circuit which includes a first transistor (Q2) responsive to negative impulses of the supply voltage and a second transistor (Q5) which is controlled by the first transistor for controlling re-firing of the power device in case of a negative pulse of the power voltage during a quenching period of the power device. The monolithic integrated circuit includes a substrate (5) having a substrate surface forming a supply voltage terminal of the power device and having a substrate voltage. An annular pocket (40) is formed in the substrate to surround or at least partially contain at least the first transistor (Q2) of the voltage limiting circuit. According to differing modes of the invention, the annular pocket (40) is biased at a voltage depending on that of the supply voltage terminal of the power device; is left at a floating potential. In one embodiment a pocket (3) is surrounded by an area of a different conductivity type (70) which has a grounded contact distributed along an emerging portion thereof.
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