High performance self balancing low cost network switching architecture based on distributed hierarchical shared
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United States of America Patent
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Sep 21, 2004
Grant Date -
Jul 18, 2002
app pub date -
Mar 19, 2002
filing date -
Jul 8, 1998
priority date (Note) -
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Abstract
A communications component comprises a first data port interface supporting a plurality of data ports transmitting and receiving data. A second data port interface supports a plurality of data ports transmitting and receiving data. An internal memory communicates with the first data port interface and the second data port interface. A memory management unit includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A plurality of independent communication channels is provided. The independent communication channels communicate data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. The memory management unit directs data from one of the first data port interface and the second data port interface to one of the internal memory and the external memory interface according to a predetermined algorithm. The predetermined algorithm allocates memory locations between the internal memory and the external memory based upon an amount of the internal memory available for each of the plurality of data ports.
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