Integration process on a SOI substrate of a semiconductor device comprising at least a dielectrically isolated well

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United States of America Patent

PATENT NO 6784042
APP PUB NO 20020146867A1
SERIAL NO

10033694

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Abstract

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An integration process in a SOI substrate of a semiconductor device having at least a dielectrically insulated well, the process including: an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto the oxide layer; a masking step, carried out onto the nitride layer using a resist layer and directed to define suitable photolithographic openings for forming at least one dielectric trench effective to provide side insulation for the well; an etching step of the nitride layer and oxide layer, as suitably masked by the resist layer, the nitride layer being used as a hardmask; a step of forming the at least one dielectric trench, which step comprises at least one step of etching the substrate, an oxidizing step of at least sidewalls of the at least one dielectric trench, and a step of filling the at least one trench with a filling material; and a step of defining active areas of components to be integrated in the well, being carried out after the step of forming the at least one dielectric trench.

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Patent Owner(s)

  • STMICROELECTRONICS S.R.L.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Salvatore, Leonardi Aci S. Antonio, IT 1 6

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