Fractional-N ADPLL with reference dithering

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United States of America Patent

PATENT NO 11658666
SERIAL NO

17708681

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Abstract

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A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.

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Patent Owner(s)

  • NXP B.V.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Misselwitz, Kai Hendrik Hanburg, DE 1 0
Moehlmann, Ulrich Moisburg, DE 19 102

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