Importance

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Abstract

A digital modulation signal is sampled by an A/D converter in a predetermined cycle. A phase interval P between a zero level crossing and the current sampling point using sampling data S.sub.i+1 at the current sampling point and sampling data S.sub.i at a sampling point which is located one point before the current sampling point. A phase P.sub.i+1 of the current sampling point is found using the phase interval P, a phase P.sub.i of the sampling point which is located one point before the current sampling point, a phase P.sub.i -1 of a sampling point which is located two points before the current sampling point and a phase P.sub.i-2 of a sampling point which is located three points before the current sampling point. A clock signal is detected using the phases P.sub.i+1 and P.sub.i. Digital data is detected using the phase interval P, the phase P.sub.i+1 and the sampling data S.sub.i at the sampling point which is located one point before the current sampling point.

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First Claim