Two-level error correcting code with sharing of check-bits
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United States of America Patent
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Sep 6, 2022
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N/A
app pub date -
Jul 10, 2020
filing date -
Jul 10, 2020
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Abstract
A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.
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