Delay locked loop
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United States of America Patent
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Aug 17, 2010
Grant Date -
Jun 12, 2008
app pub date -
Dec 27, 2006
filing date -
Sep 29, 2006
priority date (Note) -
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Abstract
A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.
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