Computer architecture having selectable, parallel and serial communication channels between processors and memory

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United States of America Patent

PATENT NO 11755060
APP PUB NO 20190041897A1
SERIAL NO

16135778

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Abstract

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A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

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Patent Owner(s)

  • WISCONSIN ALUMNI RESEARCH FOUNDATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kim, Nam Sung Middleton, US 82 655
Wang, Hao Madison, US 795 5589

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