Method for reducing extrinsic base resistance and improving manufacturability in an NPN transistor
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 14, 2004
Grant Date -
N/A
app pub date -
Nov 7, 2002
filing date -
Nov 7, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully