Address generating and decoding circuit for use in a burst-type and high-speed random access memory device which has a single data rate and a double data rate scheme
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United States of America Patent
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Mar 12, 2002
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N/A
app pub date -
Sep 1, 2000
filing date -
Sep 2, 1999
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Abstract
A burst-type random access memory device according to the present invention includes an address generator that receives an initial address to generate a sequence of burst addresses according to either one of a single data rate mode and a double data rate mode. A decoding circuit decodes the burst address thus generated. Therefore, in the memory device are automatically generated a sequence of burst addresses necessary for a sequential/interleaved burst operation of the single data rate mode and the double data rate mode.
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