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Abstract

A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n.sup.+-type region; forming field isolation areas around the n-type region; forming a PMOS gate region on the n-type region; forming a diffused n.sup.+-type contact from the upper surface of the substrate to the buried n.sup.+-type region; the contact being separated from the n-type region; forming a p-type polysilicon source on the n-type region; forming a p-type source in the n-type region; forming a p-type drain in the n-type region; and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source is connected to the gate and constitutes an emitter of the PNP transistor; the drain constitutes a collector of the PNP transistor; and the n-type region constitutes a base of the PNP transistor.

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First Claim