Clock generation for multiple clock domains
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United States of America Patent
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May 17, 2011
Grant Date -
Mar 22, 2007
app pub date -
Jul 26, 2006
filing date -
Jun 18, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated by a central clock to an appropriate frequency. By using embodiments of the invention, clock crossing circuitry between domains need not run at the highest clock frequency of the entire circuit, but rather the clock crossing circuitry need only operate at the highest frequency of the two domains sharing data.
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