Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written
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United States of America Patent
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May 11, 1999
Grant Date -
N/A
app pub date -
Jun 5, 1996
filing date -
Jun 5, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A computer system includes a memory device on the first data bus, a device that initiates on a second data bus a write transaction that can involve less than an entire cache line of data, and a bridge device that automatically converts the write transaction into one that requires an entire cache line of data and delivers the converted transaction to the first data bus.
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