Method of testing an integrated circuit having a memory and a test circuit
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United States of America Patent
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Dec 5, 2000
Grant Date -
N/A
app pub date -
Sep 13, 1999
filing date -
Mar 17, 1997
priority date (Note) -
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Abstract
The memory can be tested by the test circuit and is connected to the latter via data lines, address lines, and control lines. At least one of the control lines is connected via a controlled switching device. The switching device can be controlled via an external terminal of the integrated circuit, with the result that the signal characteristic on the corresponding line and thus the timing of the test can be influenced externally. The invention is particularly suitable for implementing self-tests of embedded memory cores.
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