Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methods

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8860117
APP PUB NO 20120273862A1
SERIAL NO

13096822

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tanzawa, Toru Adachi, JP 306 5157

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Apr 14, 2026
Fee Large entity fee small entity fee micro entity fee
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00