Vector cumulative sum instruction and circuit for implementing filtering operations

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United States of America Patent

PATENT NO 11829756
SERIAL NO

17448871

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Abstract

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A vector cumulative sum circuit can include a set of input registers, a carry-forward data source, a set of output registers, and a network of adder circuits coupling the input registers to the output registers such that the output value in a given output register is the sum of a value provided by the carry-forward data source and the input values from all of the input registers (in logical order) up to (and including) the corresponding input register. The value in the last output register can be carried forward to enable cumulative summing of a larger number of input values. The vector cumulative sum circuit can be implemented in a programmable processor, and a vector cumulative sum instruction can be defined in the instruction set. Using the vector cumulative sum circuit and instruction, filtering operations can be accelerated.

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Patent Owner(s)

  • APPLE INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ba, Seydou N Cupertino, US 5 63
Yeung, On Wa San Diego, US 6 5

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