Delay lock loop and phase locking method thereof
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United States of America
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Apr 13, 2021
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N/A
app pub date -
Sep 17, 2020
filing date -
Sep 17, 2020
priority date (Note) -
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Abstract
A delay lock loop and a phase locking method thereof are provided. The delay lock loop includes a first divider, a delay line, a frequency multiplier, a second divider, a phase detection and controlling circuit and a setting signal generator. The first divider generates a divided reference clock signal. The second divider generates a first feedback clock signal and a second feedback clock signal which are complementary by dividing an output clock signal, and generates a selected feedback clock signal by selecting the first or second feedback clock signal according to a setting signal. The phase detection and controlling circuit compares phases of the selected feedback clock signal and the divided reference clock signal to generate a delay control signal. The setting signal generator samples the divided reference clock signal by the first feedback clock signal to generate the setting signal.
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