Importance

Loading Importance Indicators...

Abstract

In a delay error improving process of a logic circuit, delay performance is certainly improved by maintaining layout and wiring path after completion of layout and wiring. A path delay is calculated by a circuit delay period calculating portion using an actual wiring information after wiring process. By the critical path extracting portion, a path not satisfying a delay performance and critical path is extracted. The cell on the critical path is re-arranged with replacing the cell having different delay performance with the same function. The overlap of the replaced cell with the other cell is solved by moving the cell. By the partial re-wiring portion, wiring connected to the replaced cell and the cells moved for overlap solving within the partial wiring region are re-wired and the layout and the wiring path of the cells not influenced by the cell replacement are maintained.

Loading the Abstract Image...

First Claim