Importance

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Abstract

An object of the present invention is to provide a buffer circuit little sensitive to a deviation from a threshold voltage of each of transistors. In order to achieve the above object, the present invention provides a typical buffer circuit comprising the following components. Namely, the buffer circuit comprises a first transistor having a first terminal connected to a current source, a second terminal connected to a first node and a control electrode connected to a first input terminal; a second transistor having a first terminal connected to the current source, a second terminal connected to a second node and a control electrode connected to a second input terminal; a third transistor having a first terminal connected to a first source node, a second terminal connected to the first node and a control electrode connected to a first output terminal; a fourth transistor having a first terminal connected to the first source node, a second terminal connected to the second node and a control electrode connected to a second output terminal; a fifth transistor having a first terminal connected to the first output terminal, a second terminal connected to the first source node and a control electrode connected to the first node; and a sixth transistor having a first terminal connected to the second output terminal, a second terminal connected to the first source node and a control electrode connected to the second node.

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First Claim